Semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface

ABSTRACT

A semiconductor device may include a semiconductor substrate and first and second spaced apart shallow trench isolation (STI) regions therein, and a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first semiconductor stringer including a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and a gate above the superlattice.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No.62/547,417 filed Aug. 18, 2017, which is hereby incorporated herein inits entirety by reference.

TECHNICAL FIELD

The present invention relates to the field of semiconductors, and, moreparticularly, to semiconductors having enhanced properties based uponenergy band engineering and associated methods.

BACKGROUND

Structures and techniques have been proposed to enhance the performanceof semiconductor devices, such as by enhancing the mobility of thecharge carriers. For example, U.S. Patent Application No. 2003/0057416to Currie et al. discloses strained material layers of silicon,silicon-germanium, and relaxed silicon and also including impurity-freezones that would otherwise cause performance degradation. The resultingbiaxial strain in the upper silicon layer alters the carrier mobilitiesenabling higher speed and/or lower power devices. Published U.S. PatentApplication No. 2003/0034529 to Fitzgerald et al. discloses a CMOSinverter also based upon similar strained silicon technology.

U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor deviceincluding a silicon and carbon layer sandwiched between silicon layersso that the conduction band and valence band of the second silicon layerreceive a tensile strain. Electrons having a smaller effective mass, andwhich have been induced by an electric field applied to the gateelectrode, are confined in the second silicon layer, thus, an n-channelMOSFET is asserted to have a higher mobility.

U.S. Pat. No. 4,937,204 to Ishibashi et al. discloses a superlattice inwhich a plurality of layers, less than eight monolayers, and containinga fractional or binary or a binary compound semiconductor layer, arealternately and epitaxially grown. The direction of main current flow isperpendicular to the layers of the superlattice.

U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short periodsuperlattice with higher mobility achieved by reducing alloy scatteringin the superlattice. Along these lines, U.S. Pat. No. 5,683,934 toCandelaria discloses an enhanced mobility MOSFET including a channellayer comprising an alloy of silicon and a second materialsubstitutionally present in the silicon lattice at a percentage thatplaces the channel layer under tensile stress.

U.S. Pat. No. 5,216,262 to Tsu discloses a quantum well structurecomprising two barrier regions and a thin epitaxially grownsemiconductor layer sandwiched between the barriers. Each barrier regionconsists of alternate layers of SiO₂/Si with a thickness generally in arange of two to six monolayers. A much thicker section of silicon issandwiched between the barriers.

An article entitled “Phenomena in silicon nanostructure devices” also toTsu and published online Sep. 6, 2000 by Applied Physics and MaterialsScience & Processing, pp. 391-402 discloses a semiconductor-atomicsuperlattice (SAS) of silicon and oxygen. The Si/O superlattice isdisclosed as useful in a silicon quantum and light-emitting devices. Inparticular, a green electroluminescence diode structure was constructedand tested. Current flow in the diode structure is vertical, that is,perpendicular to the layers of the SAS. The disclosed SAS may includesemiconductor layers separated by adsorbed species such as oxygen atoms,and CO molecules. The silicon growth beyond the adsorbed monolayer ofoxygen is described as epitaxial with a fairly low defect density. OneSAS structure included a 1.1 nm thick silicon portion that is abouteight atomic layers of silicon, and another structure had twice thisthickness of silicon. An article to Luo et al. entitled “Chemical Designof Direct-Gap Light-Emitting Silicon” published in Physical ReviewLetters, Vol. 89, No. 7 (Aug. 12, 2002) further discusses the lightemitting SAS structures of Tsu.

U.S. Pat. No. 7,105,895 to Wang et al. discloses a barrier buildingblock of thin silicon and oxygen, carbon, nitrogen, phosphorous,antimony, arsenic or hydrogen to thereby reduce current flowingvertically through the lattice more than four orders of magnitude. Theinsulating layer/barrier layer allows for low defect epitaxial siliconto be deposited next to the insulating layer.

Published Great Britain Patent Application 2,347,520 to Mears et al.discloses that principles of Aperiodic Photonic Band-Gap (APBG)structures may be adapted for electronic bandgap engineering. Inparticular, the application discloses that material parameters, forexample, the location of band minima, effective mass, etc., can betailored to yield new aperiodic materials with desirable band-structurecharacteristics. Other parameters, such as electrical conductivity,thermal conductivity and dielectric permittivity or magneticpermeability are disclosed as also possible to be designed into thematerial.

Furthermore, U.S. Pat. No. 6,376,337 to Wang et al. discloses a methodfor producing an insulating or barrier layer for semiconductor deviceswhich includes depositing a layer of silicon and at least one additionalelement on the silicon substrate whereby the deposited layer issubstantially free of defects such that epitaxial silicon substantiallyfree of defects can be deposited on the deposited layer. Alternatively,a monolayer of one or more elements, preferably comprising oxygen, isabsorbed on a silicon substrate. A plurality of insulating layerssandwiched between epitaxial silicon forms a barrier composite.

Despite the existence of such approaches, further enhancements may bedesirable for using advanced semiconductor materials and processingtechniques to achieve improved performance in semiconductor devices.

SUMMARY

A semiconductor device may include a semiconductor substrate and firstand second spaced apart shallow trench isolation (STI) regions therein,and a superlattice on the semiconductor substrate and extending betweenthe first and second STI regions. The superlattice may include aplurality of stacked groups of layers, with each group of layerscomprising a plurality of stacked base semiconductor monolayers defininga base semiconductor portion, and at least one non-semiconductormonolayer constrained within a crystal lattice of adjacent basesemiconductor portions. The semiconductor device may further include afirst semiconductor stringer including a non-monocrystalline body at aninterface between a first end of the superlattice and the first STIregion, and a gate above the superlattice.

More particularly, the first semiconductor stringer may be above thesuperlattice. Furthermore, the substrate and superlattice may includedopants therein to define spaced apart source and drain regions. In someembodiments, the semiconductor device may further include a secondsemiconductor stringer adjacent an interface between a second end of thesuperlattice and the second STI region. In one example implementation,the first semiconductor stringer may separate the first end of thesuperlattice and the first STI region.

In addition, the semiconductor stringer may comprise amorphous silicon.The semiconductor device may further include a channel stop implant inthe first semiconductor stringer. The semiconductor device may alsoinclude an oxide cap on the first semiconductor stringer. By way ofexample, the base semiconductor monolayers may comprise silicon, and theat least one non-semiconductor monolayer may comprise oxygen.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor device in accordancewith the present invention including a superlattice.

FIGS. 2A through 2D are cross-sectional views illustrating formation ofthe semiconductor device of FIG. 1 and potential difficulties associatedtherewith.

FIG. 3 is a top view of a portion of the semiconductor device of FIG. 1after gate electrode pattern and etch.

FIG. 4 is a flow diagram illustrating a process flow for making thesemiconductor device of FIG. 1.

FIGS. 5A and 5B are top views of NFET and PFET channel-stop masks usedin the method of FIG. 4.

FIGS. 6A through 6B are cross-sectional views illustrating the maskingand channel-stop implantation steps of the method of FIG. 4.

FIG. 7 is a top view of the device structure after gate electrodepattern and etch, showing the device regions where the channel-stopimplant is targeted to benefit, as part of the method of FIG. 4.

FIGS. 8A through 8C are cross-sectional views illustrating the resiststripping, gate doping, spacer formation, and source/drain doping stepsof the method of FIG. 4.

FIG. 9 is a flow diagram illustrating an alternative process flow formaking the semiconductor device of FIG. 1.

FIGS. 10A through 10B are cross-sectional views illustrating thenon-monocrystalline semiconductor etching, channel-stop implant, andgate deposition/implantation steps of the method of FIG. 9.

FIG. 11 is a top view of the device structure after the spacer formationstep of the method of FIG. 9.

FIGS. 12A and 12B are cross-sectional views of the device structureafter silicide formation taken parallel and perpendicular to the gatelayer, respectively.

FIGS. 13A and 13B are top views illustrating active area and tabchannel-stop masking steps in accordance with another alternativeprocess flow for making the semiconductor device of FIG. 1.

FIG. 14 is a greatly enlarged schematic cross-sectional view of thesuperlattice as shown in FIG. 1.

FIG. 15 is a perspective schematic atomic diagram of a portion of thesuperlattice shown in FIG. 14.

FIG. 16 is a greatly enlarged schematic cross-sectional view of anotherembodiment of a superlattice that may be used in the device of FIG. 1.

FIG. 17A is a graph of the calculated band structure from the gammapoint (G) for both bulk silicon as in the prior art, and for the 4/1Si/O superlattice as shown in FIG. 14.

FIG. 17B is a graph of the calculated band structure from the Z pointfor both bulk silicon as in the prior art, and for the 4/1 Si/Osuperlattice as shown in FIG. 14.

FIG. 17C is a graph of the calculated band structure from both the gammaand Z points for both bulk silicon as in the prior art, and for the5/1/3/1 Si/O superlattice as shown in FIG. 16.

FIGS. 18-24 are a series of schematic cross-sectional diagramsillustrating a method for performing maskless superlattice depositionfollowing STI formation in accordance an example embodiment.

FIGS. 25-27 are a series of schematic cross-sectional drawingsillustrating an alternative embodiment for performing masklesssuperlattice deposition following STI formation.

FIGS. 28A, 28B, 29-31, 32A, 32B, and 33-34 are a series of schematiccross-sectional diagrams illustrating another alternative embodiment forperforming maskless superlattice deposition following STI formation.

FIG. 35 is a table including dimensions associated with the approachillustrated in FIGS. 28A, 28B, 29-31, 32A, 32B, and 33-34.

FIG. 36 is a flow diagram illustrating method aspects associated withthe approach illustrated in FIGS. 28A, 28B, 29-31, 32A, 32B, and 33-34.

DETAILED DESCRIPTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likenumbers refer to like elements throughout, and prime and multiple primenotation are used to indicate similar elements in alternate embodiments.

The present embodiments relate to controlling the properties ofsemiconductor materials at the atomic or molecular level to achieveimproved performance within semiconductor devices. Further, theembodiments relate to the identification, creation, and use of improvedmaterials for use in the conduction paths of semiconductor devices.

Applicants theorize, without wishing to be bound thereto, that certainsuperlattices as described herein reduce the effective mass of chargecarriers and that this thereby leads to higher charge carrier mobility.Effective mass is described with various definitions in the literature.As a measure of the improvement in effective mass Applicants use a“conductivity reciprocal effective mass tensor”, M_(e) ⁻¹ and M_(h) ⁻¹for electrons and holes respectively, defined as:

${M_{e,{ij}}^{- 1}\left( {E_{F},T} \right)} = \frac{\sum\limits_{E > E_{F}}{\int_{B.Z.}{\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{i}\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{j}\frac{\partial{f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}}{\partial E}d^{3}k}}}{\sum\limits_{E > E_{F}}{\int_{B.Z.}{{f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}d^{3}k}}}$

for electrons and:

${M_{e,{ij}}^{- 1}\left( {E_{F},T} \right)} = \frac{- {\sum\limits_{E < E_{F}}{\int_{B.Z.}{\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{i}\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{j}\frac{\partial{f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}}{\partial E}d^{3}k}}}}{\sum\limits_{E < E_{F}}{\int_{B.Z.}{\left( {1 - {f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}} \right)d^{3}k}}}$

for holes, where f is the Fermi-Dirac distribution, E_(F) is the Fermienergy, T is the temperature (Kelvin), E(k,n) is the energy of anelectron in the state corresponding to wave vector k and the n^(th)energy band, the indices i and j refer to Cartesian coordinates x, y andz, the integrals are taken over the Brillouin zone (B.Z.), and thesummations are taken over bands with energies above and below the Fermienergy for electrons and holes respectively.

Applicants' definition of the conductivity reciprocal effective masstensor is such that a tensorial component of the conductivity of thematerial is greater for greater values of the corresponding component ofthe conductivity reciprocal effective mass tensor. Again Applicantstheorize without wishing to be bound thereto that the superlatticesdescribed herein set the values of the conductivity reciprocal effectivemass tensor so as to enhance the conductive properties of the material,such as typically for a preferred direction of charge carrier transport.The inverse of the appropriate tensor element is referred to as theconductivity effective mass. In other words, to characterizesemiconductor material structures, the conductivity effective mass forelectrons/holes as described above and calculated in the direction ofintended carrier transport is used to distinguish improved materials.

Using the above-described measures, one can select materials havingimproved band structures for specific purposes. One such example wouldbe a superlattice 25 material for a channel region in a semiconductordevice. A planar MOSFET 20 including the superlattice 25 in accordancewith the invention is now first described with reference to FIG. 1. Oneskilled in the art, however, will appreciate that the materialsidentified herein could be used in many different types of semiconductordevices, such as discrete devices and/or integrated circuits.

The illustrated MOSFET 20 includes a substrate 21 with shallow trenchisolation (STI) regions 80, 81 therein. More particularly, the MOSFETdevice 20 may be a complementary MOS (CMOS) device including N andP-channel transistors with respective superlattice channels, in whichthe STI regions are for electrically insulating adjacent transistors, aswill be appreciated by those skilled in the art. By way of example, thesubstrate 21 may be a semiconductor (e.g., silicon) substrate or asilicon-on-insulator (SOI) substrate. The STI regions 80, 81 may includean oxide such as silicon dioxide, for example, although other suitablematerials may be used in other embodiments.

The MOSFET 20 further illustratively includes lightly doped source/drainextension regions 22, 23, more heavily doped source/drain regions 26,27, and a channel region therebetween provided by the superlattice 25.Halo implant regions 42, 43 are illustratively included between thesource and drain regions 26, 27 below the superlattice 25. Source/drainsilicide layers 30, 31 overlie the source/drain regions, as will beappreciated by those skilled in the art. A gate 35 illustrativelyincludes a gate dielectric layer 37 adjacent the channel provided by thesuperlattice 25, and a gate electrode layer 36 on the gate dielectriclayer. Sidewall spacers 40, 41 are also provided in the illustratedMOSFET 20, as well as a silicide layer 34 on the gate electrode layer36.

Process integration of the superlattice 25 into state-of-the-art CMOSflow may require the removal of the superlattice film 25 that is formedover the STI regions 80, 81 to prevent shorting or leakage betweenadjacent device structures. Referring more particularly to FIGS. 2A-2Dthrough 3, fabrication may begin with the substrate 21 which has the STIregions 80, 81 formed therein as well as a sacrificial oxide layer 85thereon and a V_(T) implant 84 (represented by a row of “+” signs). Inthe case of a crystalline silicon superlattice, which will be describedfurther below, when the sacrificial oxide layer 85 is removed and thesuperlattice 25 is formed on the substrate 21, the silicon depositionresults in non-monocrystalline (i.e., polycrystalline or amorphous)silicon deposits 86, 87 overlying the STI regions 80, 81. However, thenon-monocrystalline silicon deposits 86, 87 typically need to be removedto prevent shorting or leakage between adjacent device structures, asnoted above.

While a relatively straightforward approach of performing masking with asingle baseline active area (AA) photoresist mask 88 (FIG. 2C) andsubsequent etching of the non-monocrystalline silicon deposits 86, 87(FIG. 2D) may be acceptable in some implementations, in other cases thiscan lead to certain difficulties. More particularly, if the mask ismisaligned (resulting in a portion of the non-monocrystalline silicondeposit 86 on STI edges being masked by the photoresist 88) or due toinsufficient over-etch during plasma etch, then portions of thenon-monocrystalline silicon deposit on the STI edges and in the STIdivots may remain unetched and hence remain as a parasitic deviceadjacent to the active device, while an active device area adjacent theSTI region (due to channel stop mask misalignment) is inadvertentlyetched leaving a gap 89. The result is that dopant creep mayunintentionally occur adjacent the non-monocrystalline silicon portion86, while non-uniform silicide and source/drain junction leakagesubstrate may occur adjacent the gap 89.

Accordingly, the masking and etching operations may advantageously bemodified to provide non-monocrystalline semiconductor stringers orunetched tabs 82, 83 with channel-stop implants in divots and edges ofthe STI regions 80, 81, as shown in FIG. 1. Again, thenon-monocrystalline semiconductor deposition occurs during the epitaxialgrowth of the semiconductor monolayers of the superlattice 25, whichover the STI regions 80, 81 results in a non-monocrystalline silicon.The non-monocrystalline stringers 82, 83 are preferably advantageouslydoped with a channel-stop implant dopant, for example, as will bediscussed further in the various fabrication examples set forth below.

Referring more particularly to FIGS. 4 through 8, a first processintegration flow for making the semiconductor device 20 is nowdescribed. Beginning with an STI wafer at Block 90, V_(T) wells areimplanted (through 150 Å pad oxide 85), at Block 91, followed by a dryetch (120 Å oxide), at Block 92. This is followed by a hydrofluoric acid(HF) exposure (SC1/100:1, 50 Å), at Block 93. In particular, the partialdry etch of the pad oxide 85 and relatively short HF exposure time mayhelp to reduce the depth of the STI divots, for example. Next, thesuperlattice film 25′ is deposited, at Block 94, which will be discussedfurther below, followed by a cleaning step (SPM/200:1, HF/RCA), at Block95.

Rather than using a single baseline AA mask as described above, in thepresent example a first, oversized N channel AA mask is formed (FIGS. 5Aand 6A), at Block 96, followed by a plasma etch of thenon-monocrystalline semiconductor material over the STI regions adjacentthe N-channel regions (Block 97) and an NFET channel-stop implant (FIG.9B) using the oversized N channel AA mask, at Block 98. In FIGS. 8A and8B, the N and P oversized masks are indicated with reference numerals 88n′ and 88 p′, respectively, and the N and P active areas are indicatedwith reference numerals 21 n′, 21 p′, respectively. Moreover, reverse Nand P wells are indicated with reference numerals 79 n′ and 79 p′,respectively.

Next, an over-sized P-channel mask is then formed (FIG. 5B), at Block99, followed by a plasma etch of the non-monocrystalline silicon overthe STI regions adjacent the P-channel region (Block 100) and the PFETchannel-stop implantation, at Block 101. The NFET and PFET channel-stopimplants are preferably performed at an angle or tilt, such as a thirtydegree angle, for example, as illustrated in FIG. 6B, although otherangles may also be used. The channel-stop implantations areillustratively shown with arrows in the drawings. By way of example,boron may be used for the NFET channel-stop implant, and arsenic orphosphorous may be used for the PFET channel-stop implant. The stringers82′, 83′ in the STI region 80′, 81′ divots and unetched silicon tabs atSTI edges are preferably highly counter-doped by the channel-stopimplant to neutralize or lessen the diffusion creep of dopants fromsource-drain regions into the non-monocrystalline silicon in the STIdivots or tabs at the corner of the channel of the device toadvantageously provide a higher diode break down voltage, higherthreshold voltage and lower off current of this parasitic edge device.The use of two different oversized masks for the P and N channel devicesadvantageously helps protect the AA alignment marks during thenon-monocrystalline silicon etching, as well as to protect each activedevice during channel stop implant of the opposite type of device.

Once the PFET channel-stop implants are completed, a pre-gate clean(SPM/HF/RCA) is performed, at Block 102 (FIG. 8A), followed by gateoxide 37′ formation (approximately 20 Å), at Block 103, andnon-monocrystalline silicon gate electrode 36 deposition andimplantation doping, at Block 104 (FIG. 8B). Gate patterning and etchingis then performed, at Block 105, followed by sidewall spacer 40′, 41′formation (e.g., 100 Å oxide) (Block 106) and LDD 22′, 23 and halo 42′,43′ implantations, at Block 107 (FIG. 8C). The spacers 40′, 41′ are thenetched (e.g., 1900 Å oxide), at Block 108. The spacer 40, 41 formationis followed by the source/drain 26′, 27′ implants and annealing (e.g.,1000° C. for 10 seconds), at Block 109, and silicide formation (Block110) to provide the device 20 shown in FIG. 1. More particularly, thesilicide may be TiSi₂ (e.g., Ti deposition, germanium implant, RTA @690° C., selective strip, followed by RTA at 750° C.).

FIGS. 12A and 12B are cross-sectional views of the device structureafter silicide formation taken parallel and perpendicular to the gatelayer 36′, respectively. In these figures, the non-monocrystallinestringers 82′, 83′ are shown with stippling to indicate that they havebeen doped with the channel-stop implant. It should be noted that thedepth of the silicon recess in the source/drain areas will depend uponthe amount of over-etch used to remove the non-monocrystalline stringersand unetched tabs (due to use of oversized active-area channel-stopmasks) 82′, 83′ in the STI divots and STI edges. Moreover, excessiverecesses may lead to increased series RSD or loss of contact between thesource/drain and the LDD regions, as will be appreciated by thoseskilled in the art. As such, these depths may require adjustmentdepending upon the given implantation.

In the above-noted process flow, the NFET and PFET masking, etching ofthe non-monocrystalline silicon 86′, 87′ over the STI regions 80′, 81′,and channel-stop implants are performed prior to gate oxidation. In analternative process flow now described with reference to FIGS. 9 through11, the above-described approach is modified so that etching of thenon-monocrystalline silicon 86′, 87′ is performed after the spaceretching step (Block 108′). Moreover, this alternative process flow alsouses an oxide or nitride cap film 78″ (FIG. 10B) over the gate electrodelayer 36″ to protect the gate polysilicon from being etched during theetching of the non-monocrystalline silicon 86″, 87″.

After dry etching (Block 92′), a cleaning step (SPM/200:1, HF (50Å)/RCA) is performed, at Block 120′, followed by an HF pre-clean (100:1)for approximately one minute. For the NFET and PFET masking depositionsteps (Blocks 96′, 99′), in the present example oversized hybridphotoresist masks are used (FIG. 10A). Additionally, after thenon-monocrystalline silicon gate electrode layer 36″ deposition (Block104′), the illustrated method includes an NSD masking step (Block 122′),followed by an N+ gate implant and cap oxide deposition, at Blocks 123′,124′. Other process variations from the above-described approach includean etching of the non-monocrystalline silicon 86″, 87″ on the STIregions 80″, 81″ (e.g., 300 Å), at Block 125′, followed by etching ofthe cap oxide layer (with a high selectivity to silicon), at Block 126′.Those remaining process steps not specifically discussed here aresimilar to those discussed above with reference to FIG. 4.

Yet another alternative process flow will now be described withreference to FIGS. 13A and 13B. This process flow uses a commonoversized AA mask for etching the non-monocrystalline silicon 86′″, 87′″on the STI regions 80′″, 81′″, followed by two separate masking stepsfor patterning tab openings. More particularly, an NFET channel-stopmask 130 n′″ and a PFET channel-stop mask 130 p′″ are used (FIG. 13B).The NFET and PFET masking steps are followed by channel-stopimplantation steps to dope the non-monocrystalline silicon in the tabopenings. The foregoing steps may be performed prior to gate oxidation.

It will be appreciated that the exemplary process flows outlined aboveadvantageously allow the etching of the non-monocrystallinesemiconductor material on the STI regions prior to gate oxide growth. Inaddition, the channel-stop implants with appropriate energy and dosewould electrically neutralize dopant diffusion from adjacent source anddrain regions into any unetched superlattice stringers inadvertentlyhiding in recessed STI divots at active area edges or tabs of thenon-monocrystalline silicon on the STI oxide, surrounding the activearea due to the over-sized active-area mask. Of course, it will beappreciated that other suitable materials and process flow parametersbesides the exemplary ones noted above may be used in differentimplementations.

Improved materials or structures for the channel region of the MOSFET 20having energy band structures for which the appropriate conductivityeffective masses for electrons and/or holes are substantially less thanthe corresponding values for silicon will now be described. Referringnow additionally to FIGS. 14 and 15, the superlattice 25 has a structurethat is controlled at the atomic or molecular level and may be formedusing known techniques of atomic or molecular layer deposition. Thesuperlattice 25 includes a plurality of layer groups 45 a-45 n arrangedin stacked relation, as noted above, as perhaps best understood withspecific reference to the schematic cross-sectional view of FIG. 14.

Each group of layers 45 a-45 n of the superlattice 25 illustrativelyincludes a plurality of stacked base semiconductor monolayers 46defining a respective base semiconductor portion 46 a-46 n and an energyband-modifying layer 50 thereon. The energy band-modifying layers 50 areindicated by stippling in FIG. 14 for clarity of illustration.

The energy-band modifying layer 50 illustratively includes onenon-semiconductor monolayer constrained within a crystal lattice ofadjacent base semiconductor portions. That is, opposing basesemiconductor monolayers 46 in adjacent groups of layers 45 a-45 n arechemically bound together. For example, in the case of siliconmonolayers 46, some of the silicon atoms in the upper or topsemiconductor monolayer of the group of monolayers 46 a will becovalently bonded with silicon atoms in the lower or bottom monolayer ofthe group 46 b. This allows the crystal lattice to continue through thegroups of layers despite the presence of the non-semiconductormonolayer(s) (e.g., oxygen monolayer(s)). Of course, there will not be acomplete or pure covalent bond between the opposing silicon layers 46 ofadjacent groups 45 a-45 n as some of the silicon atoms in each of theselayers will be bonded to non-semiconductor atoms (i.e., oxygen in thepresent example), as will be appreciated by those skilled in the art.

In other embodiments, more than one non-semiconductor layer monolayermay be possible. By way of example, the number of non-semiconductormonolayers in the energy band-modifying layer 50 may preferably be lessthan about five monolayers to thereby provide desired energyband-modifying properties.

It should be noted that reference herein to a non-semiconductor orsemiconductor monolayer means that the material used for the monolayerwould be a non-semiconductor or semiconductor if formed in bulk. Thatis, a single monolayer of a material, such as semiconductor, may notnecessarily exhibit the same properties that it would if formed in bulkor in a relatively thick layer, as will be appreciated by those skilledin the art.

Applicants theorize without wishing to be bound thereto that energyband-modifying layers 50 and adjacent base semiconductor portions 46a-46 n cause the superlattice 25 to have a lower appropriateconductivity effective mass for the charge carriers in the parallellayer direction than would otherwise be present. Considered another way,this parallel direction is orthogonal to the stacking direction. Theband modifying layers 50 may also cause the superlattice 25 to have acommon energy band structure, while also advantageously functioning asan insulator between layers or regions vertically above and below thesuperlattice. Moreover, as noted above, this structure alsoadvantageously provides a barrier to dopant and/or material bleed ordiffusion and to carrier flow between layers vertically above and belowthe superlattice 25.

It is also theorized that the superlattice 25 provides a higher chargecarrier mobility based upon the lower conductivity effective mass thanwould otherwise be present. Of course, all of the above-describedproperties of the superlattice 25 need not be utilized in everyapplication. For example, in some applications the superlattice 25 mayonly be used for its dopant blocking/insulation properties or itsenhanced mobility, or it may be used for both in other applications, aswill be appreciated by those skilled in the art.

A cap layer 52 is on an upper layer group 45 n of the superlattice 25.The cap layer 52 may comprise a plurality of base semiconductormonolayers 46. The cap layer 52 may have between 2 to 100 monolayers ofthe base semiconductor, and, more preferably between 10 to 50monolayers. Other thicknesses may be used as well.

Each base semiconductor portion 46 a-46 n may comprise a basesemiconductor selected from the group consisting of Group IVsemiconductors, Group III-V semiconductors, and Group II-VIsemiconductors. Of course, the term Group IV semiconductors alsoincludes Group IV-IV semiconductors, as will be appreciated by thoseskilled in the art. More particularly, the base semiconductor maycomprise at least one of silicon and germanium, for example.

Each energy band-modifying layer 50 may comprise a non-semiconductorselected from the group consisting of oxygen, nitrogen, fluorine, andcarbon-oxygen, for example. The non-semiconductor is also desirablythermally stable through deposition of a next layer to therebyfacilitate manufacturing. In other embodiments, the non-semiconductormay be another inorganic or organic element or compound that iscompatible with the given semiconductor processing, as will beappreciated by those skilled in the art.

It should be noted that the term “monolayer” is meant to include asingle atomic layer and also a single molecular layer. It is also notedthat the energy band-modifying layer 50 provided by a single monolayeris also meant to include a monolayer wherein not all of the possiblesites are occupied. For example, with particular reference to the atomicdiagram of FIG. 15, a 4/1 repeating structure is illustrated for siliconas the base semiconductor material, and oxygen as the energyband-modifying material. Only half of the possible sites for oxygen areoccupied.

In other embodiments and/or with different materials this one halfoccupation would not necessarily be the case as will be appreciated bythose skilled in the art. Indeed it can be seen even in this schematicdiagram, that individual atoms of oxygen in a given monolayer are notprecisely aligned along a flat plane as will also be appreciated bythose of skill in the art of atomic deposition. By way of example, apreferred occupation range is from about one-eighth to one-half of thepossible oxygen sites being full, although other numbers may be used incertain embodiments.

Silicon and oxygen are currently widely used in conventionalsemiconductor processing, and, hence, manufacturers will be readily ableto use these materials as described herein. Atomic or monolayerdeposition is also now widely used. Accordingly, semiconductor devicesincorporating the superlattice 25 in accordance with the invention maybe readily adopted and implemented, as will be appreciated by thoseskilled in the art.

It is theorized without wishing to be bound thereto, that for asuperlattice, such as the Si/O superlattice, for example, that thenumber of silicon monolayers should desirably be seven or less so thatthe energy band of the superlattice is common or relatively uniformthroughout to achieve the desired advantages. The 4/1 repeatingstructure shown in FIGS. 14 and 15, for Si/O has been modeled toindicate an enhanced mobility for electrons and holes in the Xdirection. For example, the calculated conductivity effective mass forelectrons (isotropic for bulk silicon) is 0.26 and for the 4/1 SiOsuperlattice in the X direction it is 0.12 resulting in a ratio of 0.46.Similarly, the calculation for holes yields values of 0.36 for bulksilicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of0.44.

While such a directionally preferential feature may be desired incertain semiconductor devices, other devices may benefit from a moreuniform increase in mobility in any direction parallel to the groups oflayers. It may also be beneficial to have an increased mobility for bothelectrons and holes, or just one of these types of charge carriers, aswill be appreciated by those skilled in the art. It may also bebeneficial to have a decreased carrier mobility in a directionperpendicular to the groups of layers.

The lower conductivity effective mass for the 4/1 Si/O embodiment of thesuperlattice 25 may be less than two-thirds the conductivity effectivemass than would otherwise occur, and this applies for both electrons andholes. It may be especially appropriate to dope some portion of thesuperlattice 25 in some embodiments, particularly when the superlatticeis to provide a portion of a channel as in the device 20, for example.In other embodiments, it may be preferably to have one or more groups oflayers 45 of the superlattice 25 substantially undoped depending uponits position within the device.

Referring now additionally to FIG. 16, another embodiment of asuperlattice 25′ in accordance with the invention having differentproperties is now described. In this embodiment, a repeating pattern of3/1/5/1 is illustrated. More particularly, the lowest base semiconductorportion 46 a′ has three monolayers, and the second lowest basesemiconductor portion 46 b′ has five monolayers. This pattern repeatsthroughout the superlattice 25′. The energy band-modifying layers 50′may each include a single monolayer. For such a superlattice 25′including Si/O, the enhancement of charge carrier mobility isindependent of orientation in the plane of the layers. Those otherelements of FIG. 16 not specifically mentioned are similar to thosediscussed above with reference to FIG. 14 and need no further discussionherein.

In some device embodiments, all of the base semiconductor portions 46a-46 n of a superlattice 25 may be a same number of monolayers thick. Inother embodiments, at least some of the base semiconductor portions 46a-46 n may be a different number of monolayers thick. In still otherembodiments, all of the base semiconductor portions 46 a-46 n may be adifferent number of monolayers thick.

In FIGS. 17A-17C band structures calculated using Density FunctionalTheory (DFT) are presented. It is well known in the art that DFTunderestimates the absolute value of the bandgap. Hence all bands abovethe gap may be shifted by an appropriate “scissors correction.” Howeverthe shape of the band is known to be much more reliable. The verticalenergy axes should be interpreted in this light.

FIG. 17A shows the calculated band structure from the gamma point (G)for both bulk silicon (represented by continuous lines) and for the 4/1Si/O superlattice 25 as shown in FIG. 14 (represented by dotted lines).The directions refer to the unit cell of the 4/1 Si/O structure and notto the conventional unit cell of Si, although the (001) direction in thefigure does correspond to the (001) direction of the conventional unitcell of Si, and, hence, shows the expected location of the Si conductionband minimum. The (100) and (010) directions in the figure correspond tothe (110) and (−110) directions of the conventional Si unit cell. Thoseskilled in the art will appreciate that the bands of Si on the figureare folded to represent them on the appropriate reciprocal latticedirections for the 4/1 Si/O structure.

It can be seen that the conduction band minimum for the 4/1 Si/Ostructure is located at the gamma point in contrast to bulk silicon(Si), whereas the valence band minimum occurs at the edge of theBrillouin zone in the (001) direction which we refer to as the Z point.One may also note the greater curvature of the conduction band minimumfor the 4/1 Si/O structure compared to the curvature of the conductionband minimum for Si owing to the band splitting due to the perturbationintroduced by the additional oxygen layer.

FIG. 17B shows the calculated band structure from the Z point for bothbulk silicon (continuous lines) and for the 4/1 Si/O superlattice 25(dotted lines) of FIG. 14. This figure illustrates the enhancedcurvature of the valence band in the (100) direction.

FIG. 17C shows the calculated band structure from both the gamma and Zpoint for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/Ostructure of the superlattice 25′ of FIG. 16 (dotted lines). Due to thesymmetry of the 5/1/3/1 Si/O structure, the calculated band structuresin the (100) and (010) directions are equivalent. Thus the conductivityeffective mass and mobility are expected to be isotropic in the planeparallel to the layers, i.e. perpendicular to the (001) stackingdirection. Note that in the 5/1/3/1 Si/O example the conduction bandminimum and the valence band maximum are both at or close to the Zpoint.

Although increased curvature is an indication of reduced effective mass,the appropriate comparison and discrimination may be made via theconductivity reciprocal effective mass tensor calculation. This leadsApplicants to further theorize that the 5/1/3/1 superlattice 25′ shouldbe substantially direct bandgap. As will be understood by those skilledin the art, the appropriate matrix element for optical transition isanother indicator of the distinction between direct and indirect bandgapbehavior.

Referring now additionally to FIGS. 18-24, a method of masklesssuperlattice deposition on a substrate 200 after formation of STIstructures 201 is now described. As shown in FIG. 18, a slightly thickernitride stop layer 203 is formed over an oxide layer 202 on thesubstrate 200, and adjacent portions of the oxide filled STI region 201,which is left after a CMP step. More particularly, the remaining STIportion 201 may have a thickness X of about 450 Å or more, as opposed toa conventional thickness of about 200 Å. This additional thickness issuch as to leave sufficient space for formation of a superlattice 225and a protective oxide 204 thereon as described further below. The oxidelayer 202, covers the substrate 200 beneath the nitride layer 203, andgenerally should be thick enough to serve as a CMP stop (e.g., greaterthan 150 Å thick, and more particularly greater than 200 Å thick). Thoseof skill in the art will appreciate the appropriate technique to set theCMP stop point to form the slightly thicker nitride layer 203.

The oxide layer 202 and nitride layer 203 may then be stripped off ofthe substrate 200, and the superlattice layer 225 formed thereover asshown in FIG. 19. Additionally, the protective oxide layer 204 may bethermally grown or deposited over the superlattice layer 225.

As shown in FIGS. 20 and 21, a nitride layer 205 may be deposited overthe structure to a thickness of about 450 Å, for example. This nitridelayer 205 may be planarized to the oxide layer 204 by CMP as shown inFIG. 21. Some dishing or pitting may occur during CMP as shown, but thiswill not affect the process as will be appreciated by those skilled inthe art.

As shown in FIG. 22, a plasma etch, for example, may be used to removethe superlattice layer 225 and oxide layer 204 on top of the STIstructure 201. Indeed, the prior CMP step may also be used to remove allor some of the superlattice layer 225 and oxide layer 204 on the STIstructure 201 in some implementations.

The exposed edge of the superlattice layer 225 may be re-oxidized toform an oxide cap 206, producing the intermediate structure shown inFIG. 23. In accordance with one example approach, a wet etch of thesilicon stringer or “whisker” 207 (e.g., target under-etch) may beperformed, followed by a wet oxidation. Thereafter, the remainingportion of the nitride layer 205 may be removed by wet etching, forexample, leaving the structure as shown in FIG. 24. The manufacturingprocess may continue with implanting through the oxide, etc., as will beappreciated by those skilled in the art. If desired, the remainingsuperlattice film stringer 207 on the edge of the STI structure 201 maybe removed by subjecting it to a smoothing anneal after removal of thehard oxide mask, as will also be appreciated by those skilled in theart.

An alternative to the CMP step described above with respect to FIG. 21is to re-use the STI photoresist mask 210′ and wet etch the nitride205′, as shown in FIG. 25. In this case, the photoresist mask 210′ maybe removed and a plasma etch used to expose the original STI 201′, asindicated by the dashed line 211′ in FIG. 26. This will result in theremoval of the stringer 207 discussed above, as well underlying portionsof the substrate 200′ and adjacent portions of the superlattice 225′ andoxide layer 204′ as represented by the “registration error” shown inFIG. 27. The exposed silicon (i.e., the substrate 200′ and end of thesuperlattice 225′) may then be re-oxidized to form an oxide layer 212′,followed by a wet strip of the nitride layer 205′ and subsequentprocessing. A deglazing may also be performed to etch off the oxidelayer 212′ as well.

Referring to FIGS. 28-34, the table 350 of FIG. 35, and the flow diagram360 of FIG. 36, another post-STI superlattice integration scheme is nowdescribed. Initial processing steps may include an STI module (Block361) to form the STI regions 201″ in the substrate 200″, followed by adeep well implant 213″ and threshold voltage (V_(T)) implants 214″(Block 362) through a pad oxide (e.g., 150 Å pad oxide). Further initialprocessing steps may include a dry etch of the oxide (e.g., 120 Å), atBlock 363, a sulfuric/peroxide mixture (SPM)/RCA clean (Block 364), anSC1/HF pre-clean (Block 365), superlattice 225″ deposition (Block 366),and an incoming clean, at Block 367.

The method further illustratively includes forming a thin oxide/nitridehard mask 215″ over the superlattice 225″, along with an undersizedreverse active area (AA) photoresist mask 211″, as shown in FIGS.28A-28B. Portions of the superlattice 225″ outside of the photoresistmask 211″ may then be etched away, e.g., using a plasma etch (Block370), and the photoresist mask may then be stripped away, at Block 371,as seen in FIG. 29. The amount of over-etch to clear the amorphous filmon the STI region 201″ may be set to zero, as the subsequent ringoxidation step will convert unmasked residual superlattice 225″ siliconto oxide.

An active area ring oxide 216″ may then be formed surrounding the AAregion, at Block 372 (see FIG. 30), followed by stripping of theoxide/nitride hard mask 215″ (Block 373), a pre-gate clean (Block 374),and gate dielectric 217″ formation (e.g., 20 Å), at Block 375 (see FIG.31). A step height between the gate dielectric layer 217″ and the top ofthe STI region 201″ is set by the conditions of the masked oxidationstep, amount of pre-gate clean, and initial STI protrusion/recess. Apolysilicon gate electrode layer 218″ may then be formed, at Block 376(see FIGS. 32A, 32B), followed by N+/P+ polysilicon masking and N+/P+gate implantation (Blocks 377-380). FIG. 32A is a cross-sectional viewperpendicular to the gate, while FIG. 32B is a cross-sectional viewalong the gate at the edge of the STI region 201″.

The method may further include a hard mask CVD oxide deposition, atBlock 381, gate patterning and etching (Block 382), and spacer 219″formation (e.g., 125 Å oxide), at Block 383. Halo implants 221″ andsource/drain extension implants 220″ may then be formed, at Block 384(see FIG. 33), followed by nitride or oxide spacer 222″ formation (Block385), which may optionally be performed if the notch depth at the edgeof the STI region 201″ is excessive. The superlattice 225″ mayoptionally be etched in the source/drain regions if necessary, at Block386, followed by a screen oxide formation (Block 387) and source/drainimplant 223″ formation, at Block 388.

Further processing steps illustratively includes a wet etch of the capoxide (Block 389), an RTA/spike anneal (Block 400), and a silicidemodule 401 to form source/drain and gate silicide regions 226″, 227″(see FIG. 34). More particularly, FIG. 34 is a cross-sectional viewtaken perpendicular to the gate and showing the edge of the STI region201″, in which the dashed arrow represents a smallersilicide-to-junction distance due to the present approach (˜355 Åsmaller), as will be discussed further below.

Care may be taken to avoid the notch depth at the STI 201″ edge, whichmay otherwise potentially result in a source/drain junction-to-wellshort (vertical). This should not be as much of a concern vertically,although the diagonal angle may be the biggest risk after silicideformation. Generally speaking, the junction is assumed to be ˜1000 Å.Moreover, care may be taken to avoid silicide in the notch area shortingunderneath the gate (from source-to-drain underneath the thick oxideregion). Dopant diffusion under the gate from source-to-drain mayadvantageously be reduced.

The table 350 (FIG. 35) includes exemplary surface locations relative tothe original surface for the above-described approach, although it willbe appreciated that different dimensions may be used in differentembodiments. As noted above, the net result in the present example is anapproximate 355 A (vertical) thinning in the source/drainsurface-to-junction position along the STI 201″ edge using thisapproach.

The above-described approach advantageously produces a relatively thickoxide under the gate at the STI edge. Moreover, this approach may alsobe exploited in a dual gate process, as the dual gate step may be usedfor the oxidized ring step above. Benefits of this approach may be thatit allows for the avoidance of the amorphous silicon tab when desired,avoidance of CS implants, and the potential for fewer superlattice 225″film etches (i.e., one instead of two if the superlattice film is leftin the source/drain regions).

This application is related to copending patent application entitled,“METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING NON-MONOCRYSTALLINESTRINGER ADJACENT A SUPERLATTICE-STI INTERFACE,” which is filed on thesame date and by the same assignee and inventors, the disclosure whichis hereby incorporated by reference.

Many modifications and other embodiments will come to the mind of oneskilled in the art having the benefit of the teachings presented in theforegoing descriptions and the associated drawings. Therefore, it isunderstood that such modifications and embodiments are intended to beincluded within the scope of the appended claims.

That which is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate and first and second spaced apart shallow trenchisolation (STI) regions therein; a superlattice on the semiconductorsubstrate and extending between the first and second STI regions, thesuperlattice comprising a plurality of stacked groups of layers, eachgroup of layers comprising a plurality of stacked base semiconductormonolayers defining a base semiconductor portion, and at least onenon-semiconductor monolayer constrained within a crystal lattice ofadjacent base semiconductor portions; a first semiconductor stringercomprising a non-monocrystalline body at an interface between a firstend of the superlattice and the first STI region; and a gate above thesuperlattice.
 2. The semiconductor device of claim 1 wherein the firstsemiconductor stringer is above the superlattice.
 3. The semiconductordevice of claim 1 wherein the semiconductor substrate and superlatticeinclude dopants therein to define spaced apart source and drain regions.4. The semiconductor device of claim 1 further comprising a secondsemiconductor stringer adjacent an interface between a second end of thesuperlattice and the second STI region.
 5. The semiconductor device ofclaim 1 wherein the first semiconductor stringer separates the first endof the superlattice and the first STI region.
 6. The semiconductordevice of claim 1 wherein the semiconductor stringer comprises amorphoussilicon.
 7. The semiconductor device of claim 1 further comprising achannel stop implant in the first semiconductor stringer.
 8. Thesemiconductor device of claim 1 further comprising an oxide cap on thefirst semiconductor stringer.
 9. The semiconductor device of claim 1wherein the base semiconductor monolayers comprise silicon.
 10. Thesemiconductor device of claim 1 wherein the at least onenon-semiconductor monolayer comprises oxygen.
 11. A semiconductor devicecomprising: a semiconductor substrate and first and second spaced apartshallow trench isolation (STI) regions therein; a superlattice on thesemiconductor substrate and extending between the first and second STIregions, the superlattice comprising a plurality of stacked groups oflayers, each group of layers comprising a plurality of stacked basesemiconductor monolayers defining a base semiconductor portion, and atleast one non-semiconductor monolayer constrained within a crystallattice of adjacent base semiconductor portions; a first semiconductorstringer comprising a non-monocrystalline body at an interface between afirst end of the superlattice and the first STI region; a secondsemiconductor stringer adjacent an interface between a second end of thesuperlattice and the second STI region; and a gate above thesuperlattice; the semiconductor substrate and superlattice includingdopants therein to define spaced apart source and drain regions.
 12. Thesemiconductor device of claim 11 wherein the first semiconductorstringer is above the superlattice.
 13. The semiconductor device ofclaim 11 wherein the second semiconductor stringer separates the secondend of the superlattice and the second STI region.
 14. The semiconductordevice of claim 11 further comprising a channel stop implant in thefirst and second semiconductor stringers.
 15. The semiconductor deviceof claim 11 further comprising an oxide cap on the first semiconductorstringer.
 16. The semiconductor device of claim 11 wherein the basesemiconductor monolayers comprise silicon.
 17. The semiconductor deviceof claim 11 wherein the at least one non-semiconductor monolayercomprises oxygen.
 18. A semiconductor device comprising: a semiconductorsubstrate and first and second spaced apart shallow trench isolation(STI) regions therein; a superlattice on the semiconductor substrate andextending between the first and second STI regions, the superlatticecomprising a plurality of stacked groups of layers, each group of layerscomprising a plurality of stacked base silicon monolayers defining abase silicon portion, and at least one oxygen monolayer constrainedwithin a crystal lattice of adjacent base silicon portions; a firstsemiconductor stringer comprising a non-monocrystalline body at aninterface between a first end of the superlattice and the first STIregion, the first semiconductor stringer being above the superlattice;and a gate above the superlattice.
 19. The semiconductor device of claim18 wherein the semiconductor substrate and superlattice include dopantstherein to define spaced apart source and drain regions.
 20. Thesemiconductor device of claim 18 further comprising a secondsemiconductor stringer adjacent an interface between a second end of thesuperlattice and the second STI region.
 21. The semiconductor device ofclaim 20 wherein the second semiconductor stringer separates the secondend of the superlattice and the second STI region.
 22. The semiconductordevice of claim 18 further comprising a channel stop implant in thefirst semiconductor stringer.
 23. The semiconductor device of claim 18further comprising an oxide cap on the first semiconductor stringer.